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LT3437 High Voltage 500mA, 200kHz Step-Down Switching Regulator with 100A Quiescent Current
FEATURES

DESCRIPTIO
Wide Input Range: 3.3V to 60V Load Dump (Input Transient) Protection to 80V 500mA Peak Switch Current Burst Mode(R) Operation: 100A Quiescent Current** Low Shutdown Current: IQ < 1A Burst Mode Operation Defeat 200kHz Switching Frequency Saturating Switch Design: 0.8 On-Resistance Peak Switch Current Maintained Over Full Duty Cycle Range* 1.25V Feedback Reference Voltage Easily Synchronizable Soft-Start Capability Small 10-Pin Thermally Enhanced DFN Package
The LT(R)3437 is a 200kHz monolithic buck switching regulator that accepts input voltages up to 80V. A high efficiency 500mA, 0.8 switch is included on the die along with all the necessary oscillator, control and logic circuitry. Current mode topology is used for fast transient response and good loop stability. Innovative design techniques along with a new high voltage process achieve high efficiency over a wide input range. Efficiency is maintained over a wide output current range by employing Burst Mode operation at low currents, utilizing the output to bias the internal circuitry, and by using a supply boost capacitor to fully saturate the power switch. Burst Mode operation can be defeated by a logic high signal on the SYNC pin which results in lower light load ripple at the expense of light load efficiency. Patented circuitry maintains peak switch current over the full duty cycle range.* Shutdown reduces input supply current to less than 1A. External synchronization can be implemented by driving the SYNC pin with logic-level inputs. A single capacitor from the CSS pin to the output provides a controlled output voltage ramp (soft-start). The LT3437 is available in a low profile (0.75mm) 3mm x 3mm 10-pin DFN package or a 16-Pin TSSOP Package both with exposed pad leadframes for low thermal resistance.
APPLICATIO S

High Voltage Power Conversion 14V and 42V Automotive Systems Industrial Power Systems Distributed Power Systems Battery-Powered Systems Powered Ethernet
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents including 6498466. **See Burst Mode Operation section for conditions.
TYPICAL APPLICATIO
VIN 4.5V TO 80V* VIN SHDN LT3437 VC 1500pF 25k SYNC GND FB 330pF CSS VBIAS 27pF BOOST 0.1F SW 0.1F
14V to 3.3V Step-Down Converter with 100A No Load Quiescent Current
SUPPLY CURRENT (A)
2.2F 100V CER 100H BAS21 10MQ100N VOUT 3.3V 400mA
Supply Current vs Input Voltage
200 180 160 140 120 100 80 60 40 20
3437 TA01
165k
100k
100F 6.3V TANT
*FOR INPUT VOLTAGES ABOVE 60V RESTRICTIONS APPLY
0 0 10 20 30 40 50 60 INPUT VOLTAGE (V) 70 80
3435 TA02
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Input Voltage Transient Response
VIN 20V/DIV VIN 0V VOUT 20mV/DIV AC COUPLED IOUT 250mA LOAD DUMP 50ms/DIV COLD CRANK
3437 TA03
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LT3437
ABSOLUTE
(Note 1)
AXI U RATI GS
Operating Junction Temperature Range LT3437EDD (Note 2) ....................... - 40C to 125C LT3437IDD (Note 2) ........................ - 40C to 125C LT3437EFE (Note 2) ........................ - 40C to 125C LT3437IFE (Note 2) ......................... - 40C to 125C Storage Temperature Range ................. - 65C to 125C
VIN, SHDN, BIAS, SW Operating ............................. 60V VIN, SHDN 100ms Transient, <15% Duty Cycle ....... 80V BOOST Pin Above SW ............................................ 35V BOOST Pin Voltage Operating ................................. 75V BOOST Pin 100ms Transient, <15% Duty Cycle ...... 85V SYNC, CSS, FB .......................................................... 6V
PACKAGE/ORDER I FOR ATIO
TOP VIEW SW VIN BST GND CSS 1 2 3 4 5 11 10 SHDN 9 SYNC 8 FB 7 VC 6 BIAS
DD PACKAGE 10-LEAD (3mm x 3mm) PLASTIC DFN JA = 45C/W, JC(PAD) = 10C/W
EXPOSED PAD IS GND (PIN 11) MUST BE SOLDERED TO GND (PIN 4)
ORDER PART NUMBER LT3437EDD LT3437IDD
Order Options Tape and Reel: Add #TR
DD PART MARKING LBDJ LBDK
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB = 1.25V, CSS/SYNC = 0V unless otherwise noted.
SYMBOL VSHDN ISHDN IVINS PARAMETER SHDN Threshold SHDN Input Current Minimum Input Voltage (Note 3) Supply Shutdown Current Supply Sleep Current (Note 4) IVIN Supply Quiescent Current Minimum BIAS Voltage (Note 5) SHDN = 0V, BOOST = 0V, FB/PGFB = 0V BIAS = 0V, FB = 1.35V FB = 1.35V BIAS = 0V, FB = 1.15V, VC = 0.8V, SYNC = 2V BIAS = 5V, FB = 1.15V, VC = 0.8V, SYNC = 2V

ELECTRICAL CHARACTERISTICS
CONDITIONS
SHDN = 12V
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TOP VIEW NC SW NC VIN NC BOOST NC GND 1 2 3 4 5 6 7 8 17 16 NC 15 SHDN 14 SYNC 13 NC 12 FB 11 VC 10 BIAS 9 CSS
FE PACKAGE 16-LEAD PLASTIC TSSOP
JA = 45C/W, JC(PAD) = 10C/W EXPOSED PAD IS GND (PIN 17) MUST BE SOLDERED TO GND (PIN 8)
ORDER PART NUMBER LT3437EFE LT3437IFE
FE PART MARKING 3437EFE 3437IFE
MIN 1.15

TYP 1.3 5 2.5 0.1 300 25 1.35 0.475 2.7
MAX 1.45 30 3 2 500 50 2 1 3.15
UNITS V A V A A A mA mA V
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LT3437
ELECTRICAL CHARACTERISTICS
SYMBOL IBIASS IBIAS PARAMETER BIAS Sleep Current (Note 4) BIAS Quiescent Current Minimum Boost Voltage (Note 6) Input Boost Current (Note 7) VREF IFB Reference Voltage (VREF) FB Input Bias Current EA Voltage Gain (Note 8) EA Voltage gm EA Source Current EA Sink Current VC to SW gm VC Switching Threshold VC High Clamp IPK SW VCESAT SW Current Limit Switch Saturation Voltage (Note 9) Switching Frequency Maximum Duty Cycle Minimum SYNC Amplitude SYNC Frequency Range SYNC Input Impedance ICSS CSS Current Threshold (Note 10) FB = 0V 4 240 50 10 16 ISW = 250mA ISW = 500mA

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TJ = 25C. VIN = 12V, SHDN = 12V, BIAS = 5V, FB = 1.25V, CSS/SYNC = 0V unless otherwise noted.
CONDITIONS
MIN
TYP 150 0.75 1.8 11 8
MAX 250 1 2.5 16 13 1.275 200
UNITS A mA V mA mA V nA V/V Mho
SYNC = 2V ISW = 250mA ISW = 0.5A ISW = 0.25A 3.3V < VVIN < 80V
1.225
1.25 50 900
dI(VC)= 10A FB = 1.15V FB = 1.35V VSYNC = 2V 1.5 500 15 15
650 35 30 1 500 1.75 650 200 400 170 200 95 1.5 2 700 2.1 900 400 800 240 55 55
A A A/V mV V mA mV mV kHz % V kHz k A
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT3437EDD/LT3437EFE are guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3437IDD/LT3437IFE are guaranteed and tested over the full -40C to 125C operating junction temperature range. Note 3: Minimum input voltage is defined as the voltage where switching starts. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 4: Supply input current is the quiescent current drawn by the input pin. Its typical value depends on the voltage on the BIAS pin and operating state of the LT3437. With the BIAS pin at 0V, all of the quiescent current required to operate the LT3437 will be provided by the VIN pin. With the BIAS voltage above its minimum input voltage, a portion of the total quiescent current will be supplied by the BIAS pin. Supply sleep current is
defined as the quiescent current during the "sleep" portion of Burst Mode operation. See Applications Information for determining application supply currents. Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when IBIAS is sourced into the pin. Note 6: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 7: Boost current is the current flowing into the BOOST pin with the pin held 3.3V above input voltage. It flows only during switch on time. Note 8: Gain is measured with a VC swing from 1.15V to 750mV. Note 9: Switch saturation voltage guaranteed by correlation to wafer level measurements for DD package parts. Note 10: The CSS threshold is defined as the value of current sourced into the CSS pin which results in an increase in sink current from the VC pin. See the Soft-Start section in Applications Information.
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LT3437 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency and Power Loss vs Load Current
100
60 50 40
300 250 200 150
1.26
FREQUENCY (kHz)
EFFICIENCY (%)
FB VOLTAGE (V)
VIN = 12V 90 VOUT = 3.3V TA = 25C 80 70 EFFICIENCY
30
20 10 0 0.1
POWER LOSS
1 10 100 LOAD CURRENT (mA)
SHDN Threshold
1.50 1.45 1.40
VOLTAGE (V)
ISHDN (A)
1.35 1.30 1.25 1.20
CURRENT (A)
1.15 1.10 -50 -25
50 25 0 75 TEMPERATURE (C)
Input Current vs Temperature
700 600 500
IVIN (A)
RUN MODE
IBIAS (A)
700 600
PEAK SWITCH CURRENT (mA)
400 300 200 100
SLEEP MODE VBIAS = 0V
SLEEP MODE VBIAS = 5V 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
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FB Voltage vs Temperature
500 450 400 350
Oscillator Frequency vs Temperature
250 240
1.30
1.28
POWER LOSS (mW)
230 220 210 200 190 180 170 160
1.24
100 50 0 1000
1.22
1.20 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
150 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
3437 G02
3437 G03
SHDN Pin Current
10
10 9
Shutdown Supply Current vs Temperature
8
8 7
6
6 5 4 3 VVIN = 80V VVIN = 60V
4
2
2 1
VVIN = 12V
0
100 125
0
10
20
30 VSHDN (V)
40
50
60
3437 G05
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
3437 G04
3437 G06
Bias Current vs Temperature
900 800 RUN MODE
700 600 500 400 300 200 100 800
Switch Peak Current Limit vs Temperature
500 400 300 200 100 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 SLEEP MODE
0 -50 -25
-0 25 50 75 TEMPERATURE (C)
100
125
3437 G07
3437 G08
3437 G09
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LT3437 TYPICAL PERFOR A CE CHARACTERISTICS
Soft-Start Current Threshold vs FB Voltage
35 SOFT-START DEFEATED 30 200 FREQUENCY (kHz) 25 ICSS (A) 20 15 10 5 0 0 0.2 0.6 0.8 0.4 FB VOLTAGE (V) 1.0 1.2
3437 G10
150
VOLTAGE (mV)
Supply Current vs Input Voltage
200 180 160 VOUT = 3.3V
7.5 7.0 6.5
SUPPLY CURRENT (A)
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
140 120 100 80 60 40 20 0 0 10 20 30 40 50 60 INPUT VOLTAGE (V) 70 80
Minimum On-Time
500 450 400
11 12
BOOST CURRENT (mA)
350
ON-TIME (ns)
10 9 8 7 6 100
OUTPUT VOLTAGE (V)
300 250 200 150 100 50 0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
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Oscillator Frequency vs FB Voltage
250
Switch On Voltage (VCESAT)
600 500 400 300 200 100 0 100 TJ = 25C TJ = -40C TJ = 125C
100
50
0 0 0.25 0.75 0.50 FB VOLTAGE (V) 1.00 1.25
3437 G11
400 300 200 LOAD CURRENT (mA)
500
3437 G12
Minimum Input Voltage
200 5V TO START 180 160 5V TO RUN 140 120 100 80 60 40 3.3V TO RUN 0 100 200 300 400 LOAD CURRENT (mA) 500
3437 G14
Burst Mode Threshold vs Input Voltage
VOUT = 3.3V
6.0 5.5 5.0 4.5 4.0 3.5 3.0
ENTER EXIT
3.3V TO START
20 0 0 10 40 30 20 INPUT VOLTAGE (V) 50 60
3437 G15
Boost Current vs Load Current
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 400 300 200 LOAD CURRENT (mA) 500
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Dropout Operation
VOUT = 3.3V ILOAD = 250mA BOOST DIODE = DIODES INC B1100
0 2.0 2.5 3.0 3.5 INPUT VOLTAGE (V) 4.0 4.5
3437 G18
3437 G16
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LT3437 TYPICAL PERFOR A CE CHARACTERISTICS
Dropout Operation
6 5
OUTPUT VOLTAGE (V)
VOUT = 5V ILOAD = 250mA BOOST DIODE = DIODES INC B1100
MAXIMUM DUTY CYCLE (%)
3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 6.0
93.0 92.5 92.0 91.5 -50 -25
VC VOLTAGE (V)
125
4
Maximum Sync Frequency vs Temperature
1600
MAXIMUM SYNC FREQUENCY (kHz)
1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 -50 -25
VIN = 12V VOUT = 3.3V IOUT = 100mA
50 25 0 75 TEMPERATURE (C)
Step Response
VOUT 50mV/DIV VOUT 50mV/DIV
IOUT 100mA/DIV
1ms/DIV LOAD STEP 0mA TO 200mA
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3437 G19
Maximum Duty Cycle vs Temperature
94.5 94.0 93.5 ILOAD = 250mA 0.6 0.5 0.4 0.3 0.2 0.1
VC Switching Threshold vs Temperature
50 25 0 75 TEMPERATURE (C)
100
0 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
3437 G20
3437 G21
Burst Mode Operation
VOUT 20mV/DIV AC COUPLED VOUT 20mV/DIV AC COUPLED
Burst Mode Defeated
ISW 100mA/DIV VIN = 12V VOUT = 3.3V IQ = 100A 10s/DIV
3437 G23
ISW 100mA/DIV VIN = 12V VOUT = 3.3V IQ = 1.7mA VSYNC = 3.3V 10s/DIV
3437 G24
100
125
3437 G22
Step Response
IOUT 100mA/DIV
3437 G25
1ms/DIV LOAD STEP 100mA TO 300mA
3437 G26
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LT3437
PI FU CTIO S
SW (Pin 1/Pin 2): The SW pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the SW pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum negative switch voltage allowed is -0.8V. NC (Pins 1, 3, 5, 7, 13, 16)(FE Package ONLY): No Connection. VIN (Pin 2/Pin 4): This is the collector of the on-chip power NPN switch. VIN powers the internal control circuitry when a voltage on the BIAS pin is not present. High di/dt edges occur on this pin during switch turn on and off. Keep the path short from the VIN pin through the input bypass capacitor, through the catch diode back to SW. All trace inductance on this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN. BOOST (Pin 3/Pin 6): The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional BOOST voltage allows the switch to saturate and its voltage loss approximates that of a 0.8 FET structure. GND (Pins 4, 11/Pins 8, 17): The GND pin connection acts as the reference for the regulated output, so load regulation will suffer if the "ground" end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground. Keep the path between the GND pin and the load ground short and use a ground plane when possible. The GND pin also acts as a heat sink and should be soldered (along with the exposed leadframe) to the copper ground plane to reduce thermal resistance (see Applications Information). CSS (Pin 5/Pin 9): A capacitor from the CSS pin to the regulated output voltage determines the output voltage ramp rate during start-up. When the current through the CSS capacitor exceeds the CSS threshold (ICSS), the voltage ramp of the output is limited. The CSS threshold is proportional to the FB voltage (see Typical Performance Characteristics) and is defeated for FB voltage greater than 0.9V (typical). See Soft-Start section in Applications Information for details.
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(DD/FE)
BIAS (Pin 6/Pin 10): The BIAS pin is used to improve efficiency when operating at higher input voltages and light load current. Connecting this pin to the regulated output voltage forces most of the internal circuitry to draw its operating current from the output voltage rather than the input supply. This architecture increases efficiency especially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is typically 3V. VC (Pin 7/Pin 11): The VC pin is the output of the error amplifier and the input of the peak switch current comparator. It is normally used for frequency compensation, but can also serve as a current clamp or control loop override. VC sits at about 0.45V for light loads and 1.5V at maximum load. During the sleep portion of Burst Mode operation, the VC pin is held at a voltage slightly below the burst threshold for better transient response. Driving the VC pin to ground will disable switching and place the IC into sleep mode. FB (Pin 8/Pin 12): The feedback pin is used to determine the output voltage using an external voltage divider from the output that generates 1.25V at the FB pin. When the FB pin drops below 0.9V, switching frequency is reduced, the SYNC function is disabled and output ramp rate control is enabled via the CSS pin. See the Feedback section in Applications Information for details. SYNC (Pin 9/Pin 14): The SYNC pin is used to synchronize the internal oscillator to an external signal. It is directly logic compatible and can be driven with any signal between 25% and 75% duty cycle. The synchronizing range is equal to maximum initial operating frequency up to 700kHz. When the voltage on the FB pin is below 0.9V the SYNC function is disabled. When a synchronization signal or logic-level high is present at the SYNC pin, Burst Mode operation is disabled. See the synchronizing section in Applications Information for details. SHDN (Pin 10/Pin 15): The SHDN pin is used to turn off the regulator and to reduce input current to less than 1A. The SHDN pin requires a voltage above 1.3V with a typical source current of 5A to take the IC out of the shutdown state. Exposed Pad (Pin 11/Pin 17): Ground. Must be soldered to the PCB.
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LT3437
BLOCK DIAGRA
VIN
BIAS
SYNC SHDN ANTISLOPE COMP R S
1.3V CSS BURST MODE DETECT
FB
1.25V
VC
The LT3437 is a constant frequency, current mode buck converter. This means that there is an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. A switch cycle starts with an oscillator pulse which sets the RS latch to turn the switch on. When switch current reaches a level set by the current comparator, the latch is reset and the switch turns off. Output voltage control is obtained by using the output of the error amplifier to set the switch current trip point. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180 shift will occur. The current fed system will have 90 phase shift at a much lower frequency, but will not have the additional 90 shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and gives much quicker transient response and line rejection.
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INTERNAL REF UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN 2.4V SLOPE COMP
200kHz OSCILLATOR
+
CURRENT COMP
- +
SHDN COMP
BOOST
-
SWITCH Q LATCH
DRIVER CIRCUITRY SW
SOFT-START
FOLDBACK DETECT
VC CLAMP
-
ERROR AMP GND
+
PGND
3437 BD
Figure 1. LT3437 Block Diagram
Most of the circuitry of the LT3437 operates from an internal 2.4V bias line. The bias regulator normally draws power from the VIN pin, but if the BIAS pin is connected to an external voltage higher than 3V, bias power will be drawn from the external source (typically the regulated output voltage). This improves efficiency. High switch efficiency is attained by using the BOOST pin to provide a voltage to the switch driver which is higher than the input voltage, allowing the switch to be saturated. This boosted voltage is generated with an external capacitor and diode. To further optimize efficiency, the LT3437 automatically switches to Burst Mode operation in light load situations. In Burst Mode operation, all circuitry associated with controlling the output switch is shut down, reducing the input supply current to 25A and bias input current to 150A. If lower output ripple is desired over light load efficiency, Burst Mode operation can be defeated by setting the SYNC pin voltage greater than 2V. A logic-level low on the SHDN pin disables the IC and reduces input supply current to less than 1A. External synchronization can be implemented by driving the SYNC pin with logic-level inputs.
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LT3437
APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT3437 is used to set output voltage and provide several overload protection features. The first part of this section deals with selecting resistors to set output voltage, and the remaining part talks about frequency foldback and soft-start features. Please read both parts before committing to a final design. Referring to Figure 2, the output voltage is determined by a voltage divider from VOUT to ground which generates 1.25V at the FB pin. Since the output divider is a load on the output, care must be taken when choosing the resistor divider values. For light load applications the resistor values should be as large as possible to achieve peak efficiency in Burst Mode operation. Extremely large values for resistor R1 will cause an output voltage error due to the 50nA FB pin input current. The suggested value for the output divider resistor (see Figure 2) from FB to ground (R2) is 100k or less. A formula for R1 is shown below. A table of standard 1% values is shown in Table 1 for common output voltages. R1 = R2 * VOUT - 1.25 1.25 + R2 * 50nA
VOUT SW 1 SOFT-START CSS C1 5
LT3437
200kHz OSCILLATOR
FOLDBACK DETECT
-
ERROR AMP
FB
8 R2
+
1.25V VC
7
3437 F02
Figure 2. Feedback Network
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Table 1
OUTPUT VOLTAGE (V) 2.5 3 3.3 5 6 8 10 12 R2 (k, 1%) 100 100 100 100 100 100 100 100 R1 NEAREST (1%) (k) 100 140 165 300 383 536 698 866 OUTPUT ERROR (%) 0 0 0.38 0 0.63 - 0.63 - 0.25 0.63
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More Than Just Voltage Feedback The FB pin is used for more than just output voltage sensing. It also reduces switching frequency and controls the soft-start voltage ramp rate when output voltage is below the regulated level (see the Frequency Foldback and Soft-Start Current graphs in Typical Performance Characteristics). Frequency foldback is done to control power dissipation in both the IC and in the external diode and inductor during short-circuit conditions. A shorted output requires the switching regulator to operate at very low duty cycles. As a result, the average current through the diode and inductor is equal to the short-circuit current limit of the switch (typically 500mA for the LT3437). Minimum switch on time limitations would prevent the switcher from attaining a sufficiently low duty cycle if switching frequency were maintained at 200kHz, so frequency is reduced by about 10:1 when the FB pin voltage drops below 0.4V (see Frequency Foldback graph). As the feedback voltage rises, the switching frequency increases to 200kHz with 0.95V on the FB pin. During frequency foldback, external synchronization is disabled to prevent interference with foldback operation. Frequency foldback does not affect operation during normal load conditions. In addition to lowering switching frequency, the soft-start ramp rate is also affected by the feedback voltage. Large capacitive loads or high input voltages can cause a high input current surge during start-up. The soft-start
R1
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LT3437
APPLICATIO S I FOR ATIO
function reduces input current surge by regulating switch current via the VC pin to maintain a constant voltage ramp rate (dV/dt) at the output. A capacitor (C1 in Figure 2) from the CSS pin to the output determines the maximum output dV/dt. When the feedback voltage is below 0.4V, the VC pin will rise, resulting in an increase in switch current and output voltage. If the dV/dt of the output causes the current through the CSS capacitor to exceed ICSS, the VC voltage is reduced resulting in a constant dV/dt at the output. As the feedback voltage increases, ICSS increases, resulting in an increased dV/dt until the soft-start function is defeated with 0.9V present at the FB pin. The soft-start function does not affect operation during normal load conditions. However, if a momentary short (brown out condition) is present at the output which causes the FB voltage to drop below 0.9V, the soft-start circuitry will become active. INPUT CAPACITOR Step-down regulators draw current from the input supply in pulses. The rise and fall times of these pulses are very fast. The input capacitor is required to reduce the voltage ripple this causes at the input of LT3437 and force the switching current into a tight local loop, thereby minimizing EMI. The RMS ripple current can be calculated from:
I IRIPPLE(RMS) = OUT VOUT VIN - VOUT VIN
(
)
Ceramic capacitors are ideal for input bypassing. At 200kHz switching frequency input capacitor values in the range of 2.2F to 10F are suitable for most applications. If operation is required close to the minimum input required by the LT3437, a larger value may be required. This is to prevent excessive ripple causing dips below the minimum operating voltage resulting in erratic operation. Input voltage transients caused by input voltage steps, or by hot plugging the LT3437 to a pre-powered source such as a wall adapter, can exceed maximum VIN ratings. The sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic inductance of the leads. This energy will
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cause the input voltage to swing above the DC level of input power source and it may exceed the maximum voltage rating of the input capacitor and LT3437. All input voltage transient sequences should be observed at the VIN pin of the LT3437 to ensure that absolute maximum voltage ratings are not violated. The easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low ESR input capacitor. The selected capacitor needs to have the right amount of ESR to critically damp the resonant circuit formed by the input lead inductance and the input capacitor. The typical values of ESR will fall in the range of 0.5 to 2 and capacitance will fall in the range of 5F to 50F. If tantalum capacitors are used, values in the 22F to 470F range are generally needed to minimize ESR and meet ripple current and surge ratings. Care should be taken to ensure the ripple and surge ratings are not exceeded. The AVX TPS and Kemet T495 series are surge rated. AVX recommends derating capacitor operating voltage by 2:1 for high surge applications. OUTPUT CAPACITOR The output capacitor is normally chosen by its effective series resistance (ESR) because this is what determines output ripple voltage. To get low ESR takes volume, so physically smaller capacitors have higher ESR. The ESR range for typical LT3437 applications is 0.05 to 0.2. A typical output capacitor is an AVX type TPS, 100F at 10V, with a guaranteed ESR less than 0.1. This is a "D" size surface mount solid tantalum capacitor. TPS capacitors are specially constructed and tested for low ESR, so they give the lowest ESR for a given volume. The value in microfarads is not particularly critical, and values from 22F to greater than 500F work well, but you cannot cheat Mother Nature on ESR. If you find a tiny 22F solid tantalum capacitor, it will have high ESR and output ripple voltage could be unacceptable. Table 2 shows some typical solid tantalum surface mount capacitors.
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LT3437
APPLICATIO S I FOR ATIO
E CASE SIZE AVX TPS D CASE SIZE AVX TPS C CASE SIZE AVX TPS 0.2 0.5 0.1 to 0.3 ESR MAX () 0.1 to 0.3
Table 2. Surface Mount Solid Tantalum Capacitor ESR and Ripple Current
RIPPLE CURRENT (A) 0.7 to 1.1 0.7 to 1.1
Many engineers have heard that solid tantalum capacitors are prone to failure if they undergo high surge currents. This is historically true, and type TPS capacitors are specially tested for surge capability, but surge ruggedness is not a critical issue with the output capacitor. Solid tantalum capacitors fail during very high turn-on surges which do not occur at the output of regulators. High discharge surges, such as when the regulator output is dead shorted, do not harm the capacitors. Unlike the input capacitor RMS, ripple current in the output capacitor is normally low enough that ripple current rating is not an issue. The current waveform is triangular with a typical value of 30mARMS. The formula to calculate this is: Output capacitor ripple current (RMS) IRIPPLE(RMS) = 0.29 VOUT VIN - VOUT
(
)( (L)(f)(VIN)
) = IP-P
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CERAMIC CAPACITORS Higher value, lower cost ceramic capacitors are now becoming available. They are generally chosen for their good high frequency operation, small size and very low ESR (effective series resistance). Low ESR reduces output ripple voltage but also removes a useful zero in the loop frequency response, common to tantalum capacitors. To compensate for this, a resistor RC can be placed in series with the VC compensation capacitor CC (Figure 10). Care must be taken, however, since this resistor sets the high frequency gain of the error amplifier, including the gain at the switching frequency. If the gain of the error amplifier is high enough at the switching frequency, output ripple voltage (although smaller for a ceramic output capacitor)
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may still affect the proper operation of the regulator. A filter capacitor CF in parallel with the RC/CC network, along with a small feedforward capacitor CFB, is suggested to control possible ripple at the VC pin. The LT3437 can be stabilized using a 100F ceramic output capacitor and VC component values of CC = 1500nF, RC = 25k, CF = 330pF and CFB =27pF. OUTPUT RIPPLE VOLTAGE Figure 3 shows a typical output ripple voltage waveform for the LT3437. Ripple voltage is determined by the impedance of the output capacitor and ripple current through the inductor. Peak-to-peak ripple current through the inductor into the output capacitor is: IP-P = VOUT VIN - VOUT
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(VIN )(L)(f)
(
)
For high frequency switchers the ripple current slew rate is also relevant and can be calculated from: di VIN = dt L Peak-to-peak output ripple voltage is the sum of a triwave created by peak-to-peak ripple current times ESR and a square wave created by parasitic inductance (ESL) and ripple current slew rate. Capacitive reactance is assumed to be small compared to ESR or ESL. VRIPPLE = IP-P ESR + ESL di ( )( ) ( ) dt
Example: with VIN = 12V, VOUT = 3.3V, L = 100H, ESR = 0.075, ESL = 10nH:
IP-P =
(3.3)(12 - 3.3) = 0.120A (12)(100e - 6)(200e3)
di 12 = = 0.12e6 dt 100e - 6 VRIPPLE = (0.120A)(0.075) + (10e - 9)(0.12e6) = 0.009 + 0.0012 = 10.2mVP-P
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VOUT 10mV/DIV 100F TANTALUM ESR 75m VOUT 10mV/DIV 100F CERAMIC
VSW 10V/DIV VIN = 12V VOUT = 3.3V ILOAD = 500mA L = 100H 1s/DIV
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Figure 3. LT3437 Ripple Voltage Waveform
MAXIMUM OUTPUT LOAD CURRENT Maximum load current for a buck converter is limited by the maximum switch current rating (IPK). The current rating for the LT3437 is 500mA. Unlike most current mode converters, the LT3437 maximum switch current limit does not fall off at high duty cycles. Most current mode converters suffer a drop off of peak switch current for duty cycles above 50%. This is due to the effects of slope compensation required to prevent subharmonic oscillations in current mode converters. (For detailed analysis, see Application Note 19.) The LT3437 is able to maintain peak switch current limit over the full duty cycle range by using patented circuitry to cancel the effects of slope compensation on peak switch current without affecting the frequency compensation it provides. Maximum load current would be equal to maximum switch current for an infinitely large inductor, but with finite inductor size, maximum load current is reduced by one-half peak-to-peak inductor current. The following formula assumes continuous mode operation, implying that the term on the right (IP-P/2) is less than IOUT. IOUT(MAX) = IPK -
(VOUT )(VIN - VOUT ) = IPK - IP-P 2 2(L)( f)(VIN )
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Discontinuous operation occurs when:
IOUT(DIS) VOUT VIN - VOUT 2(L)( f)(VIN )
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(
)
For VOUT = 5V, VIN = 8V and L = 68H: IOUT(MAX) = 0.5 -
(5)(8 - 5) 2(68e - 6)(200e3)(8)
= 0.5 - 0.069 = 0.431A Note that there is less load current available at the higher input voltage because inductor ripple current increases. At VIN = 15V, duty cycle is 33% and for the same set of conditions: IOUT(MAX) = 0.5 -
(5)(15 - 5) 2(68e - 6)(200e3)(15)
= 0.5 - 0.121 = 0.379 A To calculate actual peak switch current in continuous mode with a given set of conditions, use: ISW(PK) = IOUT + VOUT VIN - VOUT 2 L f VIN
( )( )( )
(
)
If a small inductor is chosen which results in discontinuous mode operation over the entire load range, the maximum load current is equal to:
IOUT(MAX) =
( )( )( ) 2(VOUT )(VIN - VOUT )
IPK 2 f L VIN
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CHOOSING THE INDUCTOR For most applications the output inductor will fall in the range of 68H to 220H. Lower values are chosen to reduce physical size of the inductor. Higher values allow
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more output current because they reduce peak current seen by the LT3437 switch, which has a 0.5A limit. Higher values also reduce output ripple voltage and reduce core loss. When choosing an inductor you might have to consider maximum load current, core and copper losses, allowable component height, output voltage ripple, EMI, fault current in the inductor, saturation and of course cost. The following procedure is suggested as a way of handling these somewhat complicated and conflicting requirements. 1. Choose a value in microhenries such that the maximum load current plus half of the inductor ripple current is less than the minimum peak switch current (IPK). Choosing a small inductor with lighter loads may result in discontinuous mode of operation, but the LT3437 is designed to work well in either mode. Assume that the average inductor current is equal to load current and decide whether or not the inductor must withstand continuous fault conditions. If maximum load current is 0.25A, for instance, a 0.25A inductor may not survive a continuous minimum peak switch current overload condition. For applications with a duty cycle above 50%, the inductor value should be chosen to obtain an inductor ripple current of less than 40% of the peak switch current. 2. Calculate peak inductor current at full load current to ensure that the inductor will not saturate. Peak current can be significantly higher than output current, especially with smaller inductors and lighter loads, so do not omit this step. Powdered iron cores are forgiving because they saturate softly, whereas ferrite cores saturate abruptly. Other core materials fall somewhere in between. The following formula assumes continuous mode of operation, but it errs only slightly on the high side for discontinuous mode, so it can be used for all conditions. IPEAK = IOUT + VOUT VIN - VOUT
( ) 2( f)(L)(VIN )
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VIN = maximum input voltage f = switching frequency, 200kHz 3. Decide if the design can tolerate an "open" core geometry like a rod or barrel, which has high magnetic field radiation, or whether it needs a closed core like a toroid, to prevent EMI problems. This is a tough decision because the rods or barrels are temptingly cheap and small, and there are no helpful guidelines to calculate when the magnetic field radiation will be a problem. 4. After making an initial choice, consider the secondary things like output voltage ripple, second sourcing, etc. Use the experts in Linear Technology's applications department if you feel uncertain about the final choice. They have experience with a wide range of inductor types and can tell you about the latest developments in low profile, surface mounting, etc.
Table 3. Inductor Selection Criteria
VENDOR/ PART NO. Coiltronics UP1B-101 UP1B-151 UP2B-221 Coilcraft D01605T-473MX D01605T-104MX D03308P-154 D03308P-224 Sumida CDRH4D28-470 CDRH4D28-101 CDRH5D28-101 47 100 100 480 290 420 0.387 1.02 0.520 3.0 3.0 3.0 47 100 150 220 450 300 600 500 1.1 2.3 0.94 1.6 1.8 1.8 3.0 3.0 100 150 220 530 460 380 1.11 1.61 1.96 5.0 5.0 5.0 VALUE (H) IDC(MAX) (mA) DCR (Ohms) HEIGHT (mm)
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Short-Circuit Considerations The LT3437 is a current mode controller. It uses the VC node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. The internal clamp on the VC node, nominally 1.5V, then acts as an output switch peak current limit. This action becomes the switch current limit specification. The maximum available output power is then determined by the switch current limit.
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A potential controllability problem could occur under short-circuit conditions. If the power supply output is short circuited, the feedback amplifier responds to the low output voltage by raising the control voltage, VC, to its peak current limit value. Ideally, the output switch would be turned on, and then turned off as its current exceeded the value indicated by VC. However, there is finite response time involved in both the current comparator and turn-off of the output switch. This results in a minimum on time tON(MIN). When combined with the large ratio of VIN to (VF + I * R), the diode forward voltage plus inductor I * R voltage drop, the potential exists for a loss of control. Expressed mathematically the requirement to maintain control is:
f * tON
VF + I * R VIN
where: f = switching frequency tON = switch on time VF = diode forward voltage VIN = Input voltage I * R = inductor I * R voltage drop If this condition is not observed, the current will not be limited at IPK but will cycle-by-cycle ratchet up to some higher value. Using the nominal LT3437 clock frequency of 200kHz, a VIN of 40V and a (VF + I * R) of say 0.7V, the maximum tON to maintain control would be approximately 90ns, an unacceptably short time. The solution to this dilemma is to slow down the oscillator to allow the current in the inductor to drop to a sufficiently low value such that the current does not continue to ratchet higher. When the FB pin voltage is abnormally low, thereby indicating some sort of short-circuit condition, the oscillator frequency will be reduced. Oscillator frequency is reduced by a factor of 10 when the FB pin voltage is below 0.4V and increases linearly to its typical value of 200kHz at a FB voltage of 0.95V (see Typical Performance Characteristics). These oscillator frequency reductions during short-circuit conditions allow the LT3437 to maintain current control
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SOFT-START For applications where [VIN/(VOUT + VF)] >10 or large input surge currents cannot be tolerated, the LT3437 soft-start feature should be used to control the output capacitor charge rate during start-up, or during recovery from an output short circuit, thereby adding additional control over peak inductor current. The soft-start function limits the switch current via the VC pin to maintain a constant voltage ramp rate (dV/dt) at the output capacitor. A capacitor (C1 in Figure 2) from the CSS pin to the regulated output voltage determines the output voltage ramp rate. When the current through the CSS capacitor exceeds the CSS threshold (ICSS), the voltage ramp of the output capacitor is limited by reducing the VC pin voltage. The CSS threshold is proportional to the FB voltage (see Typical Performance Characteristics) and is defeated for FB voltages greater than 0.9V (typical). The output dV/dt can be approximated by:
dV ICSS = dt CSS but actual values will vary due to start-up load conditions, compensation values and output capacitor selection.
CSS = GND CSS = 0.1F CSS = 0.01F VOUT 1V/DIV VIN = 12V COUT = 100F ILOAD = 200mA 1ms/DIV
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Figure 4. VOUT dV/dt
Burst Mode OPERATION To enhance efficiency at light loads, the LT3437 automatically switches to Burst Mode operation which keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. During Burst Mode operation, the LT3437 delivers short bursts of
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current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. In addition, VIN and BIAS quiescent currents are reduced to typically 25A and 150A, respectively, during the sleep time. As the load current decreases towards a no load condition, the percentage of time that the LT3437 operates in sleep mode increases and the average input current is greatly reduced, resulting in higher efficiency. The minimum average input current depends on the VIN to VOUT ratio, VC frequency compensation, feedback divider network and Schottky diode leakage. It can be approximated by the following equation: V IBIASS + IFB + IS IIN(AVG) IVINS + ISHDN + OUT VIN
SUPPLY CURRENT (A)
(
()
where IVINS = input pin current in sleep mode VOUT = output voltage VIN = input voltage IBIASS = BIAS pin current in sleep mode IFB = feedback network current IS = catch diode reverse leakage at VOUT = low current efficiency (non Burst Mode operation) Example: For VOUT = 3.3V, VIN = 12V
3.3 IIN( AVG) 25 A + 5 A + 12
(150A + 12 . 5A + 0.. 5A ) (0 . 75)
= 25 A + 5 A + 60 A = 90 A
During the sleep portion of the Burst Mode cycle, the VC pin voltage is held just below the level needed for normal operation to improve transient response. See the Typical Performance Characteristics section for burst and transient response waveforms.
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200 180 160 140 120 100 80 60 40 20 0 0 10 20 30 40 50 60 INPUT VOLTAGE (V) 70 80 VOUT = 3.3V
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Figure 5. IQ vs VIN
)
If Burst Mode operation is undesirable, it can be defeated by placing 2V or greater on the SYNC pin. When Burst Mode operation is defeated, output ripple at light loads will be reduced at the expense of light load efficiency. CATCH DIODE The catch diode carries load current during the SW off time. The average diode current is therefore dependent on the switch duty cycle. At high input to output voltage ratios, the diode conducts most of the time. As the ratio approaches unity, the diode conducts only a small fraction of the time. The most stressful condition for the diode is when the output is short circuited. Under this condition, the diode must safely handle IPEAK at maximum duty cycle. To maximize high and low load current efficiency, a fast switching diode with low forward drop and low reverse leakage should be used. Low reverse leakage is critical to maximize low current efficiency since its value over temperature can potentially exceed the magnitude of the LT3437 supply current. Low forward drop is critical for high current efficiency since the loss is proportional to forward drop. These requirements result in the use of a Schottky type diode. DC switching losses are minimized due to its low forward voltage drop, and AC behavior is benign due to its lack of a significant reverse recovery time. Schottky diodes are generally available with reverse voltage ratings of 60V, and even 100V, and are price competitive with other types.
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The use of so-called "ultrafast" recovery diodes is generally not recommended. When operating in continuous mode, the reverse recovery time exhibited by "ultrafast" diodes will result in a slingshot type effect. The power internal switch will ramp up VIN current into the diode in an attempt to get it to recover. When the diode has finally turned off, some tens of nanoseconds later, the VSW node voltage ramps up at an extremely high dV/dt, perhaps 5V to even 10V/ns! With real world lead inductances, the VSW node can easily overshoot the VIN rail. This can result in poor RFI behavior, and if the overshoot is severe enough, damage the IC itself. BOOST PIN For most applications, the boost components are a 0.1F capacitor and a BAS21 diode. The anode is typically connected to the regulated output voltage, to generate a voltage approximately VOUT above VIN to drive the output stage (Figure 6a). However, the output stage discharges the boost capacitor during the on time of the switch. The output driver requires at least 2.5V of headroom throughout this period to keep the switch fully saturated. If the output voltage is less than 3.3V, it is recommended that an alternate boost supply is used. The boost diode can be connected to the input (Figure 6b), but care must be taken to prevent the boost voltage (VBOOST = VIN * 2) from exceeding the BOOST pin absolute maximum rating. The additional voltage across the switch driver also increases power loss and reduces efficiency. If available, an independent supply can be used to generate the required BOOST voltage (Figure 6c). Tying BOOST to VIN or an independent supply may reduce efficiency, but it will reduce the minimum VIN required to start-up with light loads. If the generated BOOST voltage dissipates too much power at maximum load, the BOOST voltage the LT3437 sees can be reduced by placing a Zener diode in series with the BOOST diode (Figure 6a option). A 0.1F boost capacitor is recommended for most applications. Almost any type of film or ceramic capacitor is suitable, but the ESR should be <1 to ensure it can be fully recharged during the off time of the switch. The capacitor value is derived from worst-case conditions of 4700ns on time, 11mA boost current and 0.7V discharge
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OPTIONAL VIN VIN BOOST LT3437 GND SW VOUT VBOOST - VSW = VOUT VBOOST(MAX) = VIN + VOUT
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(6a)
VIN VIN BOOST LT3437 GND SW VOUT
VBOOST - VSW = VIN VBOOST(MAX) = 2VIN
(6b)
VIN VIN BOOST LT3437 GND SW DSS
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VDC
VOUT
VBOOST - VSW = VDC VBOOST(MAX) = VDC + VIN
(6c)
Figure 6. BOOST Pin Configurations
ripple. The boost capacitor value could be reduced under less demanding conditions, but this will not improve circuit operation or efficiency. Under low input voltage and low load conditions, a higher value capacitor will reduce discharge ripple and improve start-up operation. SHUTDOWN FUNCTION AND UNDERVOLTAGE LOCKOUT The SHDN pin on the LT3437 controls the operation of the IC. When the voltage on the SHDN pin is below the 1.2V shutdown threshold, the LT3437 is placed in a "zero" supply current state. Driving the SHDN pin above the shutdown threshold enables normal operation. The SHDN pin has an internal sink current with a typical value of 5A. In addition to the shutdown feature, the LT3437 has an undervoltage lockout function. When the input voltage is
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below 2.4V, switching will be disabled. The undervoltage lockout threshold doesn't have any hysteresis and is mainly used to insure that all internal voltages are at the correct level before switching is enabled. If an undervoltage lockout function with hysteresis is needed to limit input current at low VIN to VOUT ratios, refer to Figure 7 and the following: V V VUVLO = R1 SHDN + SHDN + ISHDN + VSHDN R3 R2 VHYST = VOUT (R1) R3
LT3437 2 VIN
+
VIN COMP
-
2.4V R1 VOUT R3 10 R2 SHDN 5A ENABLE
+
SHDN COMP
-
1.3V
Figure 7. Undervoltage Lockout
R1 should be chosen to minimize quiescent current during normal operation by the following equation: R1 =
(1.5)(ISHDN(TYP) )
12 - 2 1.5 5A
VIN - 2V
Example: R1 = R3 = R2 =
5 1.3M 1
(
()
= 1.3M
) = 6.5M (Nearest 1% 6.49M)
1.3
1.3 7 - 1.3 - 1A - 6.49M 1.3M = 408k (Nearest 1% 412k)
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See the Typical Performance Characteristics section for graphs of SHDN and VIN currents verses input voltage. SYNCHRONIZING Oscillator synchronization to an external input is achieved by connecting a TTL logic-compatible square wave with a duty cycle between 25% and 75% to the LT3437 SYNC pin. The synchronizing range is equal to initial operating frequency up to 700kHz. This means that minimum practical sync frequency is equal to the worst-case high self-oscillating frequency (240kHz), not the typical operating frequency of 200kHz. Caution should be used when synchronizing above 300kHz, because at higher sync frequencies the amplitude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs at input voltages less than twice output voltage. Higher inductor values will tend to eliminate this problem. See Frequency Compensation section for a discussion of an entirely different cause of subharmonic switching before assuming that the cause is insufficient slope compensation. Application Note 19 has more details on the theory of slope compensation. If the FB pin voltage is below 0.9V (power-up or output short-circuit conditions), the sync function is disabled. This allows the frequency foldback to operate to avoid hazardous conditions for the SW pin. If a synchronization signal or logic-level above 2V is present at the SYNC pin, Burst Mode operation is disabled. Burst Mode operation can be enabled or disabled on the fly. If no synchronization or Burst Mode defeat is required, this pin should be connected to ground. LAYOUT CONSIDERATIONS As with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum efficiency, switch rise and fall times are typically in the nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in Figure 8, must be kept as short as possible. This is implemented in the suggested layouts of Figure 9. Shortening this path will also reduce the parasitic trace
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APPLICATIO S I FOR ATIO
inductance of approximately 25nH/inch. At switch off, this parasitic inductance produces a flyback spike across the LT3437 switch. When operating at higher currents and input voltages, with poor layout, this spike can generate voltages across the LT3437 that may exceed its absolute maximum rating. A ground plane should always be used under the switcher circuitry to prevent interplane coupling and overall noise.
LT3437 VIN VIN C2 SW L1 VOUT
+
HIGH FREQUENCY CIRCULATION PATH
D1
C1
LOAD
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Figure 8. High Speed Switching Path
L1
C1
D1
C2
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FE PACKAGE TOPSIDE METAL
C1
D1
L1
C2
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DD PACKAGE TOPSIDE METAL
Figure 9. Suggested Layouts
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The VC and FB components should be kept as far away as possible from the switch and boost nodes. The LT3437 pinout has been designed to aid in this. The ground for these components should be separated from the switch current path. Failure to do so will result in poor stability or subharmonic oscillation. Board layout also has a significant effect on thermal resistance. Pin 4/Pin 10 and the exposed die pad, Pin 11/ Pin 17, are connected by a continuous copper plate that runs under the LT3437 die. This is the best thermal path for heat out of the package. Reducing the thermal resistance from Pin 4 and the exposed pad onto the board will reduce die temperature and increase the power capability of the LT3437. This is achieved by providing as much copper area as possible around the exposed pad. Adding multiple solder filled feedthroughs, under and around this pad, to an internal ground plane will also help. Similar treatment to the catch diode and coil terminations will reduce any additional heating effects. THERMAL CALCULATIONS Power dissipation in the LT3437 chip comes from four sources: switch DC loss, switch AC loss, boost circuit current, and input quiescent current. The following formulas show how to calculate each of these losses. These formulas assume continuous mode operation, and should not be used for calculating efficiency at light load currents. Switch loss:
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PSW =
RSW IOUT
( ) (VOUT ) + tEFF (1/2)(IOUT )(VIN)(f)
2
VIN
Boost current loss:
PBOOST
(VOUT )2 (IOUT /30) =
VIN
Quiescent current loss: PQ = VIN (500A) + VOUT (800A) RSW = switch resistance (1 when hot ) tEFF = effective switch current/voltage overlap time
LT3437
APPLICATIO S I FOR ATIO
(tr + tf + tIR + tIF) tr = (VIN/0.6)ns tf = (VIN/2)ns tIR = tIF = (IOUT/0.05)ns f = switch frequency
Example: with VIN = 40V, VOUT = 5V and IOUT = 250mA:
PSW
40 0.008 + 0.092 = 0.1W
(1)(0.25)2 (5) + =
/ (92)(12)(0.25)(40)(200e 3)
PBOOST
40 PQ = 40(0.0005) + 5(0.0008) = 0.024 W
(5)2 (0.25/30) = 0.005W =
Total power dissipation is: PTOT = 0.1 + 0.065 + 0.024 = 0.13W Thermal resistance for the LT3437 package is influenced by the presence of internal or backside planes. With a full plane under the package, thermal resistance will be about 45C for the FE and DD packages. No plane will increase resistance to about 150C/W. To calculate die temperature, use the proper thermal resistance number for the desired package and add in worst-case ambient temperature: TJ = TA + QJA (PTOT) With the DD package (QJA = 45C/W) at an ambient temperature of 70C: TJ = 70 + 45(0.1) = 74.5C Input Voltage vs Operating Frequency Considerations The absolute maximum input supply voltage for the LT3437 is specified at 80V. This is based solely on internal semiconductor junction breakdown effects. Due to internal power dissipation, the actual maximum VIN achievable in a particular application may be less than this. A detailed theoretical basis for estimating internal power loss is given in the section Thermal Considerations. Note
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that AC switching loss is proportional to both operating frequency and output current. The majority of AC switching loss is also proportional to the square of input voltage. For example, while the combination of VIN = 40V, VOUT = 5V at 700mA and fOSC = 200kHz may be easily achievable, simultaneously raising VIN to 80V and fOSC to 700kHz is not possible. Nevertheless, input voltage transients up to 80V can usually be accommodated, assuming the resulting increase in internal dissipation is of insufficient time duration to raise die temperature significantly. A second consideration is controllability. A potential limitation occurs with a high step-down ratio of VIN to VOUT, as this requires a correspondingly narrow minimum switch on time. An approximate expression for this (assuming continuous mode operation) is given as follows: tON(MIN) = (VOUT + VF )/VIN(fOSC) where: VIN = input voltage VOUT = output voltage VF = Schottky diode forward drop fOSC = switching frequency A potential controllability problem arises if the LT3437 is called upon to produce an on time shorter than it is able to produce. Feedback loop action will lower, then reduce, the VC control voltage to the point where some sort of cycleskipping or Burst Mode behavior is exhibited. In summary: 1. Be aware that the simultaneous requirements of high VIN, high IOUT and high fOSC may not be achievable in practice due to internal dissipation. The Thermal Considerations section offers a basis to estimate internal power. In questionable cases, a prototype supply should be built and exercised to verify acceptable operation. 2. The simultaneous requirements of high VIN, low VOUT and high fOSC can result in an unacceptably short minimum switch on time. Cycle skipping and/or Burst Mode behavior will result causing an increase in output voltage ripple while maintaining the correct output voltage.
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FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency response, the following should be remembered--the worse the board layout, the more difficult the circuit will be to stabilize. This is true of almost all high frequency analog circuits. Read the Layout Considerations section first. Common layout errors that appear as stability problems are distant placement of input decoupling capacitor and/or catch diode, and connecting the VC compensation to a ground track carrying significant switch current. In addition, the theoretical analysis considers only first order non-ideal component behavior. For these reasons, it is important that a final stability check is made with production layout and components. The LT3437 uses current mode control. This alleviates many of the phase shift problems associated with the inductor. The basic regulator loop is shown in Figure 10. The LT3437 can be considered as two gm blocks, the error amplifier and the power stage. Figure 11 shows the overall loop response. At the VC pin, the frequency compensation components used are: RC = 25k, CC = 1500pF and CF = 330pF. The output capacitor used is a 100F, 10V tantalum capacitor with typical ESR of 100m. The ESR of the tantalum output capacitor provides a useful zero in the loop frequency response for maintaining stability. This ESR, however, contributes significantly to the ripple voltage at the output (see Output Ripple Voltage in the Applications Information section). It is possible to reduce capacitor size and output ripple voltage by replacing the tantalum output capacitor with a ceramic output capacitor because of its very low ESR. The zero provided by the tantalum output capacitor must now be reinserted back into the loop. Alternatively, there may be cases where, even with the tantalum output capacitor, an additional zero is required in the loop to increase phase margin for improved transient response.
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A zero can be added into the loop by placing a resistor (RC) at the VC pin in series with the compensation capacitor, CC, or by placing a capacitor (CFB) between the output and the FB pin. When using RC, the maximum value has two limitations. First, the combination of output capacitor ESR and RC may stop the loop rolling off altogether. Second, if the loop gain is not rolled off sufficiently at the switching frequency, output ripple will perturb the VC pin enough to cause unstable duty cycle switching, similar to subharmonic oscillations. If needed, an additional capacitor (CF) can be added across the RC/CC network from the VC pin to ground to further suppress VC ripple voltage. With a tantalum output capacitor, the LT3437 already includes a resistor (RC) and filter capacitor (CF) at the VC pin (see Figures 10 and 11) to compensate the loop over the entire VIN range (to allow for stable pulse skipping for high VIN-to-VOUT ratios 10). A ceramic output capacitor can still be used with a simple adjustment to the resistor RC for stable operation (see Ceramic Capacitors section for stabilizing LT3430). If additional phase margin is required, a capacitor (CFB) can be inserted between the output and FB pin, but care must be taken for high output voltage applications. Sudden shorts to the output can create unacceptably large negative transients on the FB pin. For VIN-to-VOUT ratios < 10, higher loop bandwidths are possible by readjusting the frequency compensation components at the VC pin. When checking loop stability, the circuit should be operated over the application's full voltage, current and temperature range. Proper loop compensation may be obtained by empirical methods, as described in Application Notes 19 and 76.
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LT3437
CURRENT MODE POWER STAGE gm = 1 gm = 650 VC RC CF CC 1.6M
Figure 10. Model for Loop Response
100 80 60
GAIN (dB)
40 20 0 -20 -40 10 100 1k 10k FREQUENCY (Hz) 100k
Figure 11. Overall Loop Response
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SW R1 CFB OUTPUT
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- +
FB R2 1.25V ESR
ERROR AMP
COUT
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0 VOUT = 3.3V COUT = 100F, 0.1 -20 CF = 330pF RC = 25k -40 CC = 1500pF -60 ILOAD = 250mA -80 -100 -120 -140 -160 -180 1M
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PHASE (DEG)
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LT3437
PACKAGE DESCRIPTIO
3.50 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 6 0.38 0.10 10
PIN 1 TOP MARK (SEE NOTE 6) 5 0.200 REF 0.75 0.05 2.38 0.10 (2 SIDES) 1
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
22
U
DD Package 10-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 0.05 3.00 0.10 (4 SIDES) 1.65 0.10 (2 SIDES)
(DD10) DFN 1103
0.25 0.05 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
3437f
LT3437
PACKAGE DESCRIPTIO
3.58 (.141)
6.60 0.10 4.50 0.10
SEE NOTE 4
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 - 4.50* (.169 - .177)
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
4.90 - 5.10* (.193 - .201) 3.58 (.141) 16 1514 13 12 1110 9
2.94 (.116) 0.45 0.05 1.05 0.10
6.40 2.94 (.252) (.116) BSC
12345678 1.10 (.0433) MAX
0 - 8
0.25 REF
0.65 (.0256) BSC
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE16 (BC) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3437f
23
LT3437
TYPICAL APPLICATIO U
Supply Current vs Input Voltage
VOUT 3.3V 400mA
14V to 3.3V Step-Down Converter with 100A No Load Quiescent Current
200 180 160
VIN 4.5V TO 80V* 2.2F 100V CER VIN SHDN LT3437 VC 1500pF 25k SYNC GND FB 100k 330pF CSS VBIAS 27pF 165k 100F 6.3V TANT BOOST 0.1F SW 0.1F 100H BAS21 10MQ100N
Efficiency and Power Loss vs Load Current
100
VIN = 12V 90 VOUT = 3.3V TA = 25C 80 70 EFFICIENCY
500 450 400 350 300 250 200 150
SUPPLY CURRENT (A)
140 120 100 80 60 40
POWER LOSS (mW)
EFFICIENCY (%)
60 50 40
30
POWER LOSS
20 10
100 50
*FOR INPUT VOLTAGES ABOVE 60V SOME RESTRICTIONS MAY APPLY
3437 TA04
20 0 0 10 20 30 40 50 60 INPUT VOLTAGE (V) 70 80
0 0.1
1 10 100 LOAD CURRENT (mA)
0 1000
3437 G01
3435 TA05
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3437f LT/TP 0605 500 PRINTED IN USA
LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Controllers
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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